Senior Logic Design Engineer (4995)
Ciklum
- Місто:
- Львів
- Формат:
- повний remote
- Рівень:
- senior
- Джерело:
- jobs.dou.ua
Що робити
- Design and implement complex, configurable, low-latency RTL modules using SystemVerilog
- Develop digital logic for high-performance FPGA and ASIC applications, including signal processing, waveform generation, and real-time control
- Participate in the complete RTL development lifecycle, from architecture and microarchitecture definition to implementation and verification
- Optimize RTL designs for timing, latency, resource utilization, and power efficiency
- Perform logic synthesis, timing analysis, and optimization to meet design constraints
Що очікуємо
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline, or equivalent practical experience
- 4+ years of professional experience in FPGA or ASIC digital logic design
- Strong practical experience in RTL development using SystemVerilog (mandatory)
- Solid understanding of digital logic design, computer architecture, and RTL microarchitecture
- Experience with logic synthesis, static timing analysis (STA), and timing optimization
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