Senior FPGA Engineer (MIPI CSI-2 / Video Pipelines)
- Рівень:
- senior
- Джерело:
- djinni.co
Що робити
- Design and implement FPGA firmware in Verilog for multi-camera video processing on Lattice CrossLink-NX.
- Receive video streams from multiple sources (MIPI CSI-2, LVDS, parallel), implement stream switching and aggregate them into MIPI CSI-2 virtual channels across 2 CSI-2 outputs.
- Integrate and configure Lattice IP cores (CSI-2/D-PHY Rx/Tx, Byte-to-Pixel, Pixel-to-Byte) in Lattice Radiant.
- Implement an I2C slave interface with a documented register map for configuration and status.
- Handle clock domain crossing, timing constraints and timing closure.
Що пропонуємо
- Direct contribution to the defense of Ukraine – short path from firmware to field deployment.
- Ownership of FPGA architecture and technical decisions.
- Competitive compensation based on experience.
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