Senior FPGA Timing Specialist
- Рівень:
- senior
- Джерело:
- djinni.co
Що робити
- Analyse failed timing paths, path delays, clock skew, and routing congestion in Quartus
- Review and optimise SDC constraints and static timing analysis results
- Refactor Verilog modules and restructure pipelines or FPGA architectures
- Resolve complex timing-closure and CDC issues
- Optimise high-speed digital interfaces
Що очікуємо
- 3+ years of hands-on Verilog FPGA design experience
- Deep practical experience with Intel/Altera FPGA architecture
- Upper-Intermediate+ English level
Що пропонуємо
- 20 paid vacation days per year
- 5 paid sick leaves per year (no medical documents required)
- Personalized development plan with training compensation
- English courses compensation
- Work equipment if needed (PC / laptop / monitor)
Схожі вакансії
З блогу Trackr
Усі статті →
Знайдено через trackr.help/jobs · Канал: @trackrhelp · Бот для персональних сповіщень: @trackrhelpBot