Senior Formal Verification Engineer
- Рівень:
- senior
- Джерело:
- djinni.co
Що робити
- Define and execute formal verification strategies and methodologies for complex SoCs, IPs, and networking architectures (Switches, NICs, SmartNICs).
- Develop, implement, and maintain formal verification environments and test plans from concept to production.
- Specify formal properties, assertions, and constraints using formal tools and SystemVerilog Assertions (SVA).
- Own the formal verification environment, including setup, maintenance, and integration with simulation-based flows.
- Collaborate closely with architecture, RTL, and design teams to identify corner cases, ensure functional correctness, and drive verification sign-off.
Що очікуємо
- B.Sc. in Computer Science or Computer Engineering.
- 3+ years of industry experience in formal verification.
- Proven experience with JasperGold, VC Formal, or similar formal verification tools.
- Demonstrated ownership and maintenance of formal verification environments.
- Strong analytical and problem-solving skills.
Що пропонуємо
- 5-day working week, 8-hour working day, flexible schedule.
- No time tracker.
- Competitive salary.
- Work-life balance.
- Remote work.
Схожі вакансії
З блогу Trackr
Усі статті →
Знайдено через trackr.help/jobs · Канал: @trackrhelp · Бот для персональних сповіщень: @trackrhelpBot