The area we appreciated are:
Good control of Verilog/SV language Good understanding of the CDC, linting and EDA tools for RTL Hands-on experience with DSP designs (Multiply ACcumulate, filters, data manipulation) Decent experience with overall RTL design flow Very open and communicative Ready to learn The main areas of growth are:
AMBA protocols, especially APB, AHB, AXI High speed interfaces High frequency designs, low technology nodes Complex SOC design, integration and usage, including CPU, NOC, debug, coherency
