Physical Design Engineer (Ukraine)

Що робити

• Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below);
• In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route;
• Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing);
• In charge with all validation/qualification tasks: Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes;
• Be part of the overall Low Power solution development and implementation;