Software Engineer — RISC-V SIMD Kernels for LLMs

Що очікуємо

• Hands-on experience writing low-level compute kernels — GEMM/matmul, convolution, elementwise, reduction, or similar — regardless of whether this was for PyTorch/ATen, XLA, CUDA, ARM NEON/SVE, x86 AVX, or other hardware. The key requirement is actual kernel-writing experience, not just usage of high-level ML frameworks.
• Experience with SIMD/SIMT/vector intrinsics on any architecture (RVV, ARM NEON/SVE, x86 SSE/AVX/AVX-512) or with inline assembly, understanding how the compiler maps intrinsics to instructions etc.
• Solid understanding of memory hierarchy: cache vs. DRAM, cache lines, latency/bandwidth trade-offs, data locality, tiling/blocking for compute optimization.
• Strong interest in and willingness to optimize code for performance and memory efficiency, with the ability to identify bottlenecks and continuously improve execution speed, memory usage, and overall system efficiency.
• Strong focus on latency minimization in production inference paths — able to identify and eliminate latency-critical bottlenecks across the full execution pipeline, not just individual kernels.